1. Technical Field
The present disclosure relates to insulated-gate transistors. More specifically, the present disclosure relates to insulated-gate transistors formed on thin semiconductor substrates, as well as to a method for manufacturing such transistors.
2. Discussion of the Related Art
It is known to form, on the same solid semiconductor substrate, P-type and N-type MOS transistors. These two types of transistors are different, for example, by the doping type of their channel, by the semiconductor material forming their channel, by the material forming their gate oxide, or by the material forming their gate.
To improve the electrostatic channel control in recent technologies, the thickness of semiconductor substrates inside and on top of which electronic components are formed, as well as the thicknesses of the layers forming the components, have considerably decreased. Such is for example the case for components formed on supports of multiple-gate semiconductor type (known as “FinFET”), or formed on substrates of semiconductor-on-insulator type (SOI). In this last structure, a thin layer of semiconductor material extends on a semiconductor support with an interposed insulating layer.
It has already been provided to decrease the thickness of the upper semiconductor layer of SOI structures to a thickness on the order of a few tens of nanometers, or even of a few nanometers. This technology is known as FD-SOI, for “Fully Depleted SOI”. This form of substrate implies additional constraints for the forming of electronic components, and especially of MOS transistors. Indeed, in very thin substrates, it is not possible to define doped wells or to replace a semiconductor material region with another semiconductor material.
Other means have thus been provided to form N-type or P-type MOS transistors on FD-SOI substrates. It has in particular been provided to form insulated gates having different conductive structures, be they N-type or P-type MOS transistors on gate insulators of high dielectric constant (“high-K” dielectric materials). Indeed, with different conductive structures, gates having a variable work function, capable of defining N-type MOS transistors or P-type MOS transistors, are obtained.
Further, two manufacturing methods are conventionally used to form integrated circuits with MOS transistors: a so-called “gate-last” method activation where activation anneals at high temperature (higher than 1,000° C.) of all the doped regions are carried out before the forming of the transistor gates, and a so-called “gate-first” method where the transistor gates are formed at the substrate surface before the phase of activation anneal of all the doped regions of the integrated circuit. In the first case, the transistor gates are only submitted to anneals of interconnect integration type at temperatures which do not exceed 400° C. In the second case, the transistor gates are submitted to at least one anneal at a temperature higher than 1,000° C., which may considerably alter the gate structure and thus the work function of the gate and the transistor parameters.
Last, the gates of P-type MOS transistors have a greater work function than those of N-type MOS transistors and are more complex to manufacture.
A method for manufacturing a P-type MOS transistor compatible with FD-SOI substrates in a gate-first integration is thus needed. Further, there is a need for such a MOS transistor having decreased leakage currents.